The sigma-delta (ΣΔ) architecture has become the most popular architecture for realizing high-resolution analog-to-digital converters (ADC). FIG. 1 illustrates a generalized topology as used in a sigma delta analog-to-digital converter (ADC). The integrator stages 15, 16, 17 depicted in FIG. 1 can use continuous-time (C/T or CT) digital-to-analog converters (DACs) or discrete-time (D/T or DT) DACs. The continuous-time solution incorporates a current DAC (IDAC) in the feedback path, whereas a discrete-time solution incorporates a switched-capacitor (S/C) DAC in the feedback path.
Continuous-time Sigma Delta ADCs have received much attention in the last couple of years for applications that require signal bandwidths of several MHz. Continuous-time ADCs are more favourable over switched-capacitor ADCs due to their lower power requirements. Other advantages include better noise immunity due to their inherent anti-aliasing properties, which is especially advantageous in RF receivers. Also, the technology trend towards very deep submicron processes dictates lower power supply voltages. Switched capacitor based circuits require boot-strapping techniques to drive the switches in order to extend the dynamic range and sampling rates of the converter. Continuous-time ADCs avoid such problems and much higher signal bandwidths can be attained.
Despite the advantages mentioned above in using continuous-time ΣΔ ADCs, audio band ADC implementations have remained in the discrete time domain. This is because discrete time ADCs achieve relatively high linearity, they are very tolerant of clock jitter, and as high signal bandwidths are not required moderate sampling rates can be employed in sigma-delta based ADCs. Also, chopper stabilisation can be readily employed in discrete-time to remove the flicker noise especially problematic in deep submicron MOS devices and the filter coefficients are very stable. The paper “A 114-dB 68-mW Chopper-stabilized stereo multibit audio ADC in 5.62 mm2”, by YuQing Yang; Chokhawala, A.; Alexander, M.; Melanson, J.; Hester, D.; IEEE Journal of Solid-State Circuits, Vol. 38, Issue 12, Dec. 2003 Pages 2061–2068 describes the use of chopping in conjunction with a multi-bit discrete-time ADC. However, chopper stabilization is restricted to the op-amp used for the integrator stage.
U.S. Pat. No. 5,039,989 (Welland et al.) uses chopping in conjunction with a continuous-time converter, but only with a single-bit ADC and single-bit feedback-DAC solution. Single-bit continuous-time ADCs are especially sensitive to jitter and the arrangement presented in U.S. Pat. No. 5,039,989 is unsuitable for a multi-bit converter.
A discrete-time ADC implementation would seem to be advantageous over a continuous-time ADC for audio band applications for the reasons mentioned already. However, relatively large signal ranges, e.g. 2 Vrms, used within audio television are outside the voltage range that switched-capacitor based circuits implemented in deep sub-micron technology can easily interface to. In this case, the only solution would be to attenuate the input signal and thus surrender valuable dynamic range. Even after attenuating the input signal, anti-alias filtering circuitry and buffering circuitry would be required to drive the switched-capacitor input stage. OEMs typically demand that this functionality is provided on-chip, inevitably leading to an increased die cost along with deteriorated noise performance.
There is a desire to use a continuous-time front-end ΣΔ modulator in this application as it avoids having to attenuate, anti-alias filter and buffer the input. However, in using a continuous-time front-end ΣΔ ADC there remain issues of the continuous-time ΣΔ modulator being sensitive to clock jitter and distortion which is produced as a result of the inter-symbol interference within the IDAC. The technology trend towards very deep sub-micron processes dictates lower power supply voltages. Continuous-time ADCs are well suited to these processes. However, one limitation which has inhibited the use of continuous-time ADCs is flicker noise. Implementing a Continuous-time ADC in sub-micron technology would require the DC biasing current source to have a large area in order to achieve low noise. This is because flicker noise is inversely proportional to the area of a device. The input and output devices of the amplifiers would also require a large area for achieving high performance. However, a lower area solution would be desirable.
Accordingly, the present invention seeks to provide an improved continuous-time sigma-delta ADC.